1. Field of the Invention
The present invention relates to an automatic deskew system and method for use in high-speed, parallel interconnections for digital systems, including high performance microprocessor systems, memory systems, and input/output (xe2x80x9cI/Oxe2x80x9d) systems.
2. Description of Background Art
As data communication speeds increase in high performance digital systems and as the length of signal lines, for example copper or optical cables or printed circuit board traces, connecting the components of such high performance digital systems increases, the skew of the data arrival time at the receiving end of each signal line for parallel interconnections becomes significant. The skew on each signal line results from differences in the characteristics and length of each cable, connector or printed circuits board trace. Moreover, the skew is aggravated by the high data transfer rates.
Conventional deskew circuits exist to solve the problem of inter-bit skew on high-speed, parallel interconnections; however, conventional deskew circuits typically make use of an analog, device called a variable delay line (xe2x80x9cVDLxe2x80x9d). A VDL adds an amount of delay to a one bit skewed data input so as to align such one bit data input with other data input bits on parallel signal lines.
Conventional VDLs have numerous problems. First, it is difficult and expensive to make a VDL that can operate over a wide range of inputs and with a high degree of accuracy. The wider the range of operation and the better the accuracy of the VDL, the greater the number of delay elements, typically buffers, required. These buffers occupy space and increase overall chip size and pin connections and are, therefore, expensive.
Second, it is difficult to create a VDL with linear behavior. Linearity in a VDL is a desirable characteristic. If, for example, a VDL produces a two microsecond delay for an input value of one and a four microsecond delay given input value two, the VDL should produce a six microsecond delay given an input value of three. If instead the VDL produced a ten microsecond delay given input value of three, then the wrong amount of delay would be added to the skewed input data line and misalignment among the parallel input data lines would result.
Third, VDLs are not temperature-stable. For example, a VDL operating in low temperature conditions may output a delay of two microseconds given a certain input and a delay of three microseconds given the same input if operating in high temperature conditions. Thus, if a conventional deskew circuit containing a VDL is placed in a temperature variable environment, the performance of the VDL is unreliable. As a result, an incorrect amount of delay gets added to the one bit skewed input, resulting in misalignment of signals on parallel lines.
In addition to adding delay to correct for skew on parallel data input lines, conventional deskew circuits may also perform the task of xe2x80x9cunfoldingxe2x80x9d. Specifically, in the case of a one to four unfolding circuit, four consecutive bits of a data signal are converted to an output signal of four bits width, one bit per output and each output bit having a rate one fourth that of the input. A purpose for slowing the rate of the input and unfolding is to make the design of the core logic circuit in the digital system easier. Generally the core logic circuit in such a system is quite complicated, thus a slower operation frequency facilitates design. Conventional deskew circuits typically perform the tasks of adding delay and unfolding sequentially.
Given the foregoing, there is a need for an automatic deskew system for use in high-speed, parallel interconnections for digital systems that: (i) operates over a wide range of inputs with accuracy; (ii) is suitable in temperature-variable environments; and (iii) performs unfolding.
The present invention includes a system and method for performing automatic deskew tuning and alignment across high-speed, parallel interconnections in a high performance digital system to compensate for inter-bit skew. Rather than using a VDL, the present invention includes digital elements, such as registers and multiplexers, which result in a simpler, more robust system capable of operating over a wider range of input values with greater accuracy and over a broader range of temperatures. In addition, the present invention performs a one to four unfolding of the signal on each interconnection.
A system in accordance with the present invention may include a deskew controller and a plurality deskew subsystems. The deskew controller computes the amount of delay needed to correct the skew on each interconnection and feeds a different (or appropriate) delay value to each deskew subsystem located at the receiving end of each interconnection.
Each deskew subsystem includes a clock recovery subsystem, a retiming subsystem and two coarse deskew subsystems. The clock recovery subsystem corrects skew that is less than the period of time for the transmission of one bit of information on an interconnection (xe2x80x9cone bit timexe2x80x9d or xe2x80x9cTxe2x80x9d).
The retiming subsystem and the coarse deskew subsystem collectively correct for any remaining skew by adding delay in integer multiples of one bit time, T, from 0T to 7T. The retiming subsystem and the coarse deskew subsystems collectively perform a one to four unfolding of the input signal.
The final output of the automatic deskew system is a one to four unfolding of each data input signal line and an alignment of all data on parallel interconnections in the digital system.
The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter.